The invention relates to a method of forming an isolation layer in a semiconductor device, and more particularly to a method of forming an isolation layer in a semiconductor device, which can reduce or prevent a bent phenomenon of an active region caused by a compressive stress exerted on an isolation layer.
As the integration of a semiconductor device is increased, a smaller pattern is formed, and widths of an active region and an isolation region become narrowed due to the smaller pattern.
In particular, the narrower the width of a trench formed in the isolation region, the more the aspect ratio is increased, which can make it difficult to perform a gap-fill process to form an insulating layer (for example, a high density plasma (HDP) layer). To improve the gap-fill characteristic, a technique for forming a spin-on-dielectric (SOD) layer has been developed. The conventional HDP layer has a low step coverage characteristic. The aspect ratio of the trench is increased so that an upper portion of the trench is covered with the HDP layer, while a lower portion of the trench is not filled completely. As a result, a void can be generated in the isolation layer. Due to such a void, etchant can penetrate easily into the isolation layer during a subsequent etching process, causing a defect of the isolation layer. In order to solve the above-described problem, a lower portion of the trench is filled with the SOD layer to reduce an aspect ratio. The isolation layer can be then formed of the HDP layer. The SOD layer is formed in the liquid state, and a heat treatment process is performed to oxidize and densify the SOD layer prior to forming the HDP layer.
Although the SOD layer is densified through the heat treatment process, the SOD layer has a high etching selection ratio in a range of six (6) times to ten (10) times higher than that of the conventional HDP layer. Accordingly, when an etching process is performed after forming a subsequent HDP layer, etchant can penetrate into the SOD layer.
Referring to FIG. 1A and FIG. 1B, etchant can penetrate into the SOD layer via the HDP layer to generate a void in the isolation layer. If the void is generated in the isolation layer, a strength unbalance between a region of the isolation layer in which the void is generated and another region of the isolation layer in which no void is generated can cause the active region to bend. The bent active region causes a layer formed on an upper portion of the active region to become unstable, and an electrical characteristic of the semiconductor device can be deteriorated.